Dr. Shasanka Sekhar Rout

Education

Work Experience

Research Interests

• Analog VLSI design
• Analog and RF CMOS circuit design
• VLSI signal processing

Publications

1. S. S. Rout, S. Acharya and K. Sethi, “A low phase noise gm-boosted DTMOS VCO design in 180 nm CMOS technology,” Karbala International Journal of Modern Science, Elsevier, Iraq, vol. 4, no. 2, pp. 228-236, Mar. 2018, doi.org/10.1016/j.kijoms.2018.03.001.
2. S. S. Rout, S. K. Mohapatra and K. Sethi, “Design of cascode mixer based on bulk injection and switched biasing techniques in 180 nm CMOS process for a high performance receiver front end,” Journal of Low Power Electronics (JOLPE), American Scientific Publishers, US vol. 14, no. 1, pp. 49-56, Mar. 2018, doi.org/10.1166/jolpe.2018.1527.
3. S. S. Rout and K. Sethi, “A high gain, low power and low noise down conversion mixer using 0.18 μm CMOS process,” Modelling, Measurement and Control Series A. General Physics and Electrical Applications, AMSE, France, vol. 90, no. 4, pp. 353-367, July. 2017.
4. S. S. Rout and K. Sethi, “A high gain and low noise CMOS Gilbert mixer with improved linearity based on MGTR and switched biasing technique,” ICTACT Journal on Microelectronics, ICT Academy of Tamil Nadu (ICTACT), vol. 2, no. 4, pp. 311-314, Jan. 2017, doi: 10.21917/ijme.2016.0054.
5. S. S. Rout, R. K. Barik and S. K. Dwibedi, “A low voltage and low noise CMOS RF bulk injection mixer for UWB system application,” International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE), India, vol. 3, pp. 445-452, Apr. 2014.
6. D. Tripathy, S. S. Rout and K. Sethi, “A low power noise cancelling LNA for UWB receiver front end,” 2015 IEEE Power, Communication and Information Technology Conference (PCITC), SOA University, Bhubaneswar, India, pp. 442-446, Oct. 2015, doi: 10.1109/PCITC.2015.7438206.
7. S. S. Rout, D. Tripathy, and K. Sethi, “An improved bulk injection cascode Mixer for receiver front end design,” 2nd National Conference on Devices and Circuits-2016, IEEE ED-NIST Student Chapter, Berhampur, India, pp. 37-41, Feb. 2016.
8. S. S. Rout and K. Sethi, “Design of high gain and low noise CMOS Gilbert cell mixer for receiver front end design,” 15th IEEE International Conference on Information Technology (ICIT)-2016, IIIT, Bhubaneswar, India, pp. 1-5, Dec. 2016, doi: 10.1109/ICIT.2016.16.
9. S. S. Rout and K. Sethi, “A high conversion gain and low flicker noise Gilbert mixer design in 180 nm CMOS process,” 14th IEEE India Council International Conference (INDICON), IIT Roorkee, pp. 1-5, India, Dec. 2017, doi: 10.1109/INDICON.2017.8487552.
10. Participated in the AICTE sponsored staff development programme on “Environment and Waste Management” at ABIT, Cuttack. (25th May-7th June 2011)
11. Pparticipated in the training programme on “Faculty Induction Programme” by NITTTR, Kolkata. (21-26 May 2011)
12. Participated in the workshop on “Quality Enhancement for Teachers in Engineering Education through NPTEL” at IIT, Kharagpur. (16-17 Nov. 2011)
13. Participated in the workshop on “Advance VLSI Design using Cadence EDA Tools” at University of Calcutta. (3-4 July 2015)
14. Participated in the workshop on “High performance Digital signal Processing and Implementation” at IIT, Bhubaneswar (15-17 Dec. 2015).
15. Participated in the workshop on “Internet of Things devices and Sensor Networks” at VSSUT, Burla. (22-23 Oct. 2016)
16. Participated in the “6th IEEE EDS Mini-Colloquium on Device and Reliability” at NIST, Berhampur. (20th Feb. 2016)
17. Participated twice in the workshop on “Cadence Training” at BPUT, Rourkela. (4-8 April 2016, 8-13 Aug. 2016)
18. Participated in the workshop on “Awareness Generation on IPR” at VSSUT, Burla. (17-18 Mar. 2017)
19. Student organizer in a one week Workshop on “MATLAB AND SIMULINK” conducted by VSSUT, Burla. (13-17 Nov. 2017)
20. Presented and exhibited the research findings in the “MRS-2017” at VSSUT, Burla.
21. Participated in a two week ISTE STTP on “CMOS, Mixed Signal and RF VLSI Design” conducted by IIT, Kharagpur. (30 Jan.- 4 Feb. 2017)
22. Attended in the “8th IEEE EDS Mini-Colloquium on Quantum Electronics” at NIST, Berhampur. (23th Feb. 2018)
23. Attended in the “4th National Conference on Devices and Circuits (NCDC-2018)” at NIST, Berhampur. (24th Feb. 2018)
24. Participated in a one week Faculty Development Programme on “DSP & SENSOR” organized by Electronics and ICT Academies supported by Ministry of Electronics and Information Technology, (MeitY), Goi. (10-14 Dec. 2018)
25. Completed the “BSNL Summer Practical Training Course”. (7th May-8th June 2007)