Mr. Manoj Kumar Senapati

Education

Work Experience

Research Interests

• Hardware and sostware design of electronics circuits & VLSI.

Publications

1. Abhyarthana Bisoyi, Mitu Baral, Manoja Kumar Senapati, “Comparison of a 32-Bit Vedic Multiplier With a Conventional Binary Multiplier”, IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT) , on May 2014, pp. 1762- 1765, ISBN No. 978-1-4799-3914-5/14
2. Swastik Ranjan Nanda,Subhasree Subhasmita Senapati,Manoj Kumar Senapati, “FPGA Implementation of UART Protocol with Flexible Baud Rate”, 3rd National Conference on Devices and Circuits(NCDC-2017) on March, 2017,pp.79-82, ISBN: 978-93-83060-18-4
3. Manoj Kumar Senapati, M.Suresh, Mitu Baral “A Hardware Model of a Robot Cart Using FPGA for Aerospace application” 4th National Conference on Devices and Circuits(NCDC-2018) on Feb, 2018,pp.46-50, ISBN: 978-93-83060-16-0
4. Manoj Kumar Senapati, Asish Kumar Gouda, Priyadarshan Pattanayak “Interfacing of SD Card with FPGA” 4th National Conference on Devices and Circuits(NCDC-2018) on Feb, 2018,pp.75-78, ISBN: 978-93-83060-16-0
5. Manoj Kumar Senapati, Mukesh Kumar Sukla,Subhadeepta Tripathy, Rolit Pathy “Design and Implementation of 8-bit soft-core Microcontroller on FPGA” 4th National Conference on Devices and Circuits(NCDC-2018) on Feb, 2018,pp.86-91, ISBN: 978-93-83060-16-0
6. Manoj Kumar Senapati, Mitu Baral, M.Suresh, Konapala Alekhya, Lipishree Madala “A Hardware Model of a wireless controlled Quiz Buzzer system Using FPGA” 4th National Conference on Devices and Circuits(NCDC-2018) on Feb, 2018,pp.101-105, ISBN: 978-93-83060-16-0
7. One day Seminar on“VLSI Design using Tanner Tool” on 5th November 2007 at NIST, Berhampur.
8. One day seminar in IEEE EDS Mini-Collequium on “Nano Electronics” held on 30th December 2010 at NIST, Berhampur.
9. Two week ISTE Workshop on “Analog Electronics” conducted by Indian Institute of Technology, Kharagpur from 4th – 14th June, 2013 under the National Mission on Education Though ICT (MHRD).
10. Two weeks workshop on “Real Time Embedded System Design for Signal Processing Application – An FPGA Design Approach” jointly organized by IEEE EDS NIST Students Chapter and National Institute of Science and Technology, Berhampur, Odisha from 12th – 23rd July, 2013.
11. Short Term Course on “FPGA Prototyping using Verilog” on June 16th to 28th, 2014
12. Two Day National Workshop on “Embeded Design Flow Using Xilinx Zynq Soc” at NIST, Berhampur on 9th – 10th April 2015.
13. Two Day National Workshop on “Advanced Embeded System Design onZynq using Vivado targeting Zed Board” at NIT, Tircy on 27th – 28th August, 2015
14. Two Day Workshop on “High Performance Digital Signal Processing System Design and Implementation” at IIT Bhubaneswar on 15-17 December 2015.
15. Two day hand on workshop on “System design on Zynq Using SDSoc” at IIT Madras, Chennai on 2nd -3rd January 2016.
16. Two Day FDP on “ ASIC Verification” at MAVEN Silicon ,Bangalore, on 3rd-4th September, 2016.
17. One week Short Term Course on “ ARM Cortex M4 based Embedded System” conducted by E & ICT Academy, at IIT Roorkee from 17th-22th January 2017.
18. Two week ISTE Short Term Course on “ CMOS, Mixed Signal and Radio frequency VLSI design” conducted by IIT Kharagpur on 30th January to 4thth February 2017 at NIST.
19. Three day workshop on “VLSI and Embedded System Design(VESD-2017)” conducted by IIT Bhubaneswar on 13th -15th October 2017
20. One week workshop on “DSP & SENSORS” jointly organized by Electronics and ICT Academies through National Knowledge Network under the “Scheme of financial assistance for setting up of Electronics and ICT Academics” of the Ministry of Electronics and Information Technology (MeitY) Government of India from 10th -14th December 2018