Mr. M. Suresh

Education

Work Experience

Research Interests

• VLSI Low power design

Publications

1. A survey of VLSI Architectures for FFT computations in Signal and Image Processing Applications, The Icfai University Journal of Telecommunications, vol 1, No. 1, pp. 79-88, 2009, C K Jha, M Suresh, and A K Panda.
2. Hardware efficient Architectures for FPGA implementation of FFT Algorithm in multi carrier transmission system, GITAM Journal of Information, Communication Technology, Vol. 2, No. 1, pp.38-43, 2009, C K Jha, M Suresh and A K Panda.
3. A Novel Flash Analog-to-Digital Converter Design using Cadence Tool, IEEE, 978-0-7695-3845, 2009, pp: 28-30. M Suresh, Santoshi Sahu, Kiran Sadangi and A K Panda, Digital Object Finder 10.1109/ARTCom.2009.111
4. Power Analysis and Simulation of Low Power Gated-Clock Design of LFSR using 250nm Technology International Journal of Computational Intelligence Research and Applications,2009, Vol. 3, No.1, January - June , pp. 157-161A. K. Panda, Mr. M. Suresh,Mr. Mukesh Sukla.
5. Design of Arithmetic Circuits Using Reversible Logic Gates and Power Dissipation Calculation, selected for the conference "International Symposium on Electronic System Design (ISED) 2010" 20-22 December 2010, Bhubaneswar, India, M Suresh, DR. A K Panda, et al. pp. 85 - 90, 978-1-4244-8979-4, Digital
6. Design and Comparison of Low Power High Speed CMOS Full Adder Circuits with Different Logic Styles, Proceeding of National Conference on Advances in Communication Technologies NCACT-2010 3-4 December 2010 GITAM University, Vishakatnam, K P Sahu, U S Sahu, M Suresh, Dr. Ajit Kumar Panda.
7. Design of Reversible Logic Gates Using 0.12um Technology, Proceeding of 1st National Conference on Electronics Communication and Instrumention e-Manthan-2010, College of Science and Engineering, Jhansi, 2-3 April, 2010 pp 203-206.
8. FPGA Design of a fast 32-bit Floating Point Multiplier Unit , "International Conference on Devices, Circuits and Systems (ICDCS) 15-16 March, 2012 M Suresh, Dr. Ajit Kumar Panda, Anna Jain, Baisakhi Das. pp. 545-567. IEEE explore 978-1-4577-1545-7, Digital object finder 10.1109/ ICDCSyst.2012.6188744
9. Recent Trends in Microwave/MM wave Generator and Receiver, Proceedings of CSPIT-2002, UCE, Burla, pp. 6-9, 2002, A. Patnaik, M. Suresh, and A. K. Panda.
10. Molecular memory & Sigmatropic shift Arun Ku Padhy, M. Suresh & Debajani Majhi14th Annual conference of Orissa Chemical Society, Bhawanipatna, Orissa, India, 2000.
11. Molecular memory & Hydrogen shift Arun K Padhy & M.Suresh 3rd National Symposium in Chemistry, Chandigarh, India, 2001.
12. An Investigation on Interfacing between two Processors through the Wireless Medium to have an ad-hoc Network, Proceedings of National Conference on ‘EmergingTrends in the Computing and Communication 2008, NIT, Hamirpur, 30 – 31, Dec, 2008.M. Suresh, S. Azad.
13. Physical Design and Simulation of Content Addressable Memory (CAM) using Tanner Tool, Proceeding of National Seminar on Recent Advances in Science and Technology, April 20-21, 2012, Neha Sinha, Saurav Kumar Agarwal, M Suresh.
14. A Comparitive Analysis of High Performance 1-bit Full Adder Cell using Tanner Tool, Proceeding of National Seminar on Recent Advances in Science and Technology,April 20-21,2012, Deepshika, Saloni, M Suresh.
15. Multimode Chemical Transducers Arun Ku Padhy, M.Suresh & Debajani Majhi 19th Annual Conference of Indian Council of Chemists, Shimoga, India, 2000.
16. A. Patnaik, M. Suresh, A. K. Panda: "Recent Trends in Microwave/MM wave Generator and Receiver,"Proceedings of Communication, Signal Processing and Information Technology (CSPIT) - 2002, February 2002, Burla (India).